Author: Denis Avetisyan
A new framework harnesses the power of artificial intelligence to automate semiconductor device design and optimization, dramatically accelerating the path to future technologies.
AgenticTCAD, a multi-agent system leveraging large language models, achieves IRDS-2024 specifications for a 2nm nanosheet FET in just 4.2 hours.
As semiconductor technology continues to scale, efficient device design is increasingly constrained by the complexity of design-technology co-optimization. This work introduces AgenticTCAD: A LLM-based Multi-Agent Framework for Automated TCAD Code Generation and Device Optimization, a novel approach leveraging large language models and an open-source dataset to automate the process. We demonstrate that AgenticTCAD can achieve International Roadmap for Devices and Systems (IRDS)-2024 specifications for a 2nm nanosheet FET in just 4.2 hours, a significant reduction from the 7.1 days required by human experts-but can this framework be extended to tackle even more complex device architectures and optimization challenges?
Deconstructing the Limits of Transistor Design
The relentless drive to increase transistor density, vividly illustrated by the development of Nanowire-based Field-Effect Transistors (NS-FETs), necessitates increasingly sophisticated device simulations. As feature sizes shrink towards the sub-nanometer scale, traditional modeling approaches falter, unable to accurately capture the complex quantum mechanical effects and intricate geometries that dominate device behavior. Accurate prediction of performance now requires computationally intensive simulations-incorporating 3D structures, strain effects, and quantum confinement-to model carrier transport, electrostatics, and reliability. These simulations aren’t merely about verifying designs; they are becoming integral to the design process itself, allowing engineers to explore vast parameter spaces and optimize devices before fabrication – a crucial step in meeting the ambitious performance targets outlined in the IRDS-2024 roadmap.
The relentless pursuit of miniaturization, as outlined in the IRDS-2024 roadmap, presents a significant challenge to established semiconductor design practices. Historically, iterative refinement by engineers has driven performance gains, but the complexity of modern nanoscale transistors now dwarfs previous generations. Optimizing for power, speed, and reliability requires navigating an immense design space, where even minor parameter adjustments can have cascading effects. Traditional methods, relying heavily on manual tuning and simplified models, are increasingly inadequate to address these intricate interdependencies and meet the stringent specifications demanded by next-generation devices. Consequently, achieving the performance targets outlined in IRDS-2024 necessitates a fundamental shift toward automated design exploration and more sophisticated modeling techniques capable of accurately capturing the nuances of nanoscale transistor behavior.
The relentless drive towards increasingly miniaturized transistors is encountering a significant hurdle: the optimization of device parameters is rapidly becoming unmanageable through conventional methods. Historically, engineers refined transistor designs via iterative manual adjustments, but the complexity of next-generation architectures, like the Non-Silicon Field-Effect Transistor (NS-FET), has rendered this approach impractical. The sheer number of interacting variables-channel composition, gate oxide thickness, doping profiles, and more-creates a parameter space too vast for efficient exploration by human intuition. This bottleneck isn’t merely a matter of increased workload; it actively impedes innovation, delaying the realization of devices capable of meeting the stringent performance targets outlined in the International Roadmap for Semiconductors 2024 (IRDS-2024). Consequently, advanced computational techniques and automated design tools are no longer optional, but essential for sustaining progress in semiconductor technology.
Automating the Design Process: An Agentic Approach
AgenticTCAD utilizes Large Language Models (LLMs) to automate tasks within Technology Computer-Aided Design (TCAD) simulation, specifically focusing on device design and optimization. The framework integrates LLMs to interpret design requirements and translate them into the necessary parameters for TCAD simulations. This automation extends to the iterative process of simulation, analysis, and parameter adjustment, enabling a closed-loop optimization workflow without requiring continuous manual intervention. By leveraging the predictive capabilities of LLMs, AgenticTCAD streamlines the design process, reducing the time and resources needed to achieve desired device characteristics and performance targets.
AgenticTCAD employs an LLM to process natural language descriptions of desired device characteristics, effectively converting qualitative design goals into quantitative simulation parameters. This process involves parsing the input text to identify key performance indicators (KPIs) and constraints, then mapping these to specific TCAD model settings such as channel length, doping concentration, oxide thickness, and bias voltages. The LLM utilizes a trained knowledge base to establish these correlations, allowing it to automatically generate the necessary input files for TCAD simulations without requiring manual parameter specification or expert interpretation of design intent. This automated translation streamlines the design process and facilitates rapid exploration of the design space.
AgenticTCAD facilitates closed-loop optimization of device designs by iteratively adjusting simulation parameters based on results, thereby significantly reducing development time. In a demonstrated case, the framework achieved International Roadmap for Semiconductors (IRDS)-2024 specifications for a 2nm Nanowire FET (NS-FET) design in 4.2 hours. This represents a substantial decrease compared to the 7.1 days required for equivalent optimization performed by human experts, indicating a potential order-of-magnitude improvement in design cycle efficiency.
From Structure to Simulation: The Engine Under the Hood
The initial step in the TCAD simulation process utilizes Sentaurus Structure Editor (SDE) to define the precise three-dimensional geometry of the semiconductor device under investigation. This geometric definition is then discretized into a mesh comprised of interconnected elements, forming the basis for numerical analysis. The mesh density and element type are critical parameters, influencing both the accuracy of the simulation and computational cost; finer meshes generally yield more accurate results but require significantly more processing time. SDE allows for the creation of complex device structures, including variations in layer thickness, doping concentrations, and contact placements, all of which are translated into the discrete mesh used for subsequent electrical simulations.
Sentaurus Device (SDevice) utilizes numerical methods to solve the fundamental semiconductor equations – Poisson’s equation, the continuity equations, and the transport equations – on the discretized mesh created in Sentaurus Structure Editor. This solution process calculates the spatial distribution of electrical potential, carrier concentrations, and current densities within the device. By accurately modeling these physical phenomena, SDevice predicts key electrical characteristics including current-voltage (I-V) curves, capacitance-voltage (C-V) profiles, and switching speeds. The simulation accounts for effects such as carrier mobility, recombination, and quantum mechanical tunneling, providing a comprehensive assessment of device performance before fabrication.
AgenticTCAD optimization resulted in a device with an on-state current (I_{on}) of 2.31 x 10-3 A/μm, representing a 2.94x improvement over the established performance target. Crucially, this enhanced performance was achieved while maintaining off-state current (I_{off}) levels compliant with IRDS-2024 specifications. Furthermore, the optimized designs demonstrate a subthreshold swing (SSS) of 60.38 mV/dec, exceeding the required threshold of 72 mV/dec, indicating improved switching efficiency.
Refining Intelligence: Training the LLM for Design Autonomy
Supervised fine-tuning is essential for adapting a large language model (LLM) to the specific task of generating Technology Computer-Aided Design (TCAD) scripts. Utilizing the open-source TCAD dataset, the LLM learns to correlate natural language instructions with the corresponding TCAD commands and syntax. This process involves training the model on a labeled dataset of input prompts and their correct TCAD script outputs, allowing it to minimize prediction errors and improve the accuracy of script generation. The quality and size of the TCAD dataset directly impact the LLM’s ability to produce syntactically correct and functionally valid TCAD simulations, and this fine-tuning stage is crucial for achieving reliable automation of device design and optimization workflows.
The AgenticTCAD framework leverages large language models (LLMs) with a two-tiered approach to maximize performance. Open-source models, specifically Qwen2.5-14B-Instruct, establish a robust base for script generation and initial device exploration. Subsequently, the integration of commercially available models, such as DeepSeek V3.1, provides enhancements to the framework’s capabilities, including improved accuracy, more complex design space navigation, and potentially faster convergence towards optimal device configurations. This hybrid approach balances accessibility with state-of-the-art performance, allowing for both research and practical application of LLM-driven TCAD automation.
Utilizing a data-driven methodology, the Large Language Model (LLM) can systematically investigate potential semiconductor device designs without explicit human guidance. This autonomous exploration involves iteratively generating TCAD (Technology Computer-Aided Design) scripts, simulating resulting device characteristics, and analyzing the outcomes to refine subsequent design iterations. The LLM leverages the training data – comprising TCAD scripts and corresponding device performance data – to predict the impact of parameter adjustments and intelligently navigate the multi-dimensional design space. This process facilitates the identification of device configurations that meet or exceed specified performance targets, potentially uncovering novel designs beyond those traditionally considered by human engineers.
The pursuit of automated design, as demonstrated by AgenticTCAD, isn’t merely about speed-though achieving IRDS-2024 specifications for a 2nm nanosheet FET in under five hours is a notable feat. It’s about systematically dismantling established workflows to reveal underlying principles. This echoes the sentiment of Carl Friedrich Gauss: “If others would think as hard as I do, they would not consider me so hard to understand.” AgenticTCAD embodies this intellectual rigor, meticulously breaking down the complex task of device optimization into manageable agent interactions. The framework doesn’t simply apply existing knowledge; it actively tests the boundaries of TCAD simulation and design-technology co-optimization, exposing limitations and forging new pathways for innovation. It is a structured challenge to the status quo, a methodical unraveling of complexity.
Beyond Automation: The Ghosts in the Machine
The successful deployment of AgenticTCAD exposes a fundamental truth: automation isn’t about replicating expertise, but about systematically provoking failure. The framework doesn’t solve the design problem; it rapidly cycles through iterations until a viable solution emerges, revealing the constraints and vulnerabilities inherent in the simulation space. This raises the question: what previously unarticulated assumptions are baked into the open-source dataset, and how might these biases propagate through future designs? A bug, after all, is the system confessing its design sins.
The 4.2-hour optimization for a 2nm nanosheet FET is a demonstration of speed, certainly, but speed reveals little about optimality. The true challenge lies not in achieving IRDS-2024 specifications, but in exceeding them – pushing the boundaries of what’s considered physically possible. Future work must focus on integrating AgenticTCAD with inverse design techniques, actively exploring the parameter space beyond the current performance envelope.
Ultimately, the value of this framework may not be in its ability to generate designs, but in its capacity to generate questions. Each successful optimization is merely a temporary respite, a localized minimum in a vast, unexplored landscape. The system will inevitably encounter problems it cannot solve, and it is in those failures that the most valuable insights reside.
Original article: https://arxiv.org/pdf/2512.23742.pdf
Contact the author: https://www.linkedin.com/in/avetisyan/
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2026-01-05 00:17